NetNews Offline 2/NetNews Offline Volume 2.iso/news/comp/sys/amiga/programmer/7372

Internet Message Format | 1996-08-05 | 3.5 KB

Path: informatik.tu-muenchen.de!fischerj
From: [e-mail] (Juergen "Rally" Fischer)
Newsgroups: comp.sys.amiga.programmer
Subject: Re: CHIP RAM speed test resul
Date: 15 Apr 1996 13:54:05 GMT
Organization: Technische Universitaet Muenchen, Germany
Distribution: world
Message-ID: <4ktkdt$[e-mail]>
References: <4j6jv0$[e-mail]> <[e-mail]> <[e-mail]> <4k1kk3$[e-mail]> <4k2fbl$[e-mail]>
NNTP-Posting-Host: hphalle5.informatik.tu-muenchen.de
Originator: [e-mail]


In article <4k2fbl$[e-mail]>, [e-mail] (Michael van Elst) writes:
|> [e-mail] (Juergen "Rally" Fischer) writes:
|>
|> >ok, so why my 020 needs _12_ cycles , i.e. _846_ ns (!!!!) to load a
|> >byte/.w/.l from chipmem ?
|>
|> Maybe chip-bus contention ?

no. all chipdma off. "normal" dma-load (8 planes lores) won't change much.
movem-read can get near to something like 10 cycles (because it does
5 cyles in fastmem ;)
So acess in multiples of 2 cycles, max speed 8 cycles/acess.

|>
|> >why AGA got the curious quality that _any_ kind of chipmem acess is
|> >just 2 times slower than it is in fastmem ?
|>
|> This obviously depends on the speed of your fastmem.

my fastmem is 0waitstate to a 020-14, I should have said "just 2 times
slower than max possible 020 acess". Still courious, how it manages to
make any kind of acess 2 times slower.

I always had the impression that acess times are constants, not factors ;)

|>
|> >that's unlogic, because any acess should be delayed by a fix amount
|> >of time. but: load 6 -> 12 cycles (difference: 6), store 4 -> 8 cycles
|> >(difference: 4).
|>
|> No. Writes are usually faster because a write cycle can complete while
|> the CPU continues with internal operation. A read must complete because
|> the CPU needs the data fetched.

my measurements include continous stores ;) I know a write to chipmem is
2 cycles if it is followed by 3 reg,reg operations ;)

It is really courious. Only the 6 cycles move.l (chip),(chip) is
not done x2 to 12 cycles, because this would be against the
"min 8 cycles chipmemacess" rule, so it is done in 16 cycles.

2 rules:

a) ideal acess x2 (well, on a synced 020-14).
b) if a) is less than "number of acesses x 8 cycles" then increase
   to that number (this should be true for all cpus, meaning 8 14-MHz
   cycles of course).

|>
|> >: perfectly aligned with the chip bus timing, or you would need a FIFO
|> >: device to store the fetched data for when CPU could take it.
|>
|> >again, beeing no expert at all, I can't stand the feeling that this FIFO
|> >would be just another $0.2 TTLs. again, what about walker ?
|>
|> No, it would be more than $0.2 (and very few TTL parts cost $0.2
|> anyway).

Well, IMHO they should do it in walker. Like they did in A3000.
Lots of people will use it for gaming, it will make sense.

|> >Am I missing something ?
|>
|> Yes. "Adding some TTLs" needs lots of board space. And that is a price
|> issue.

ah :\
what about a inovative $3 sandwitch platine carrying all the TTLs ? ;)

|>
|>
|>
|> --
|>                                 Michael van Elst
|>
|> Internet: [e-mail]
|>                                 "A potential Snark may lurk in every tree."
------------------------------------------------------------------------
   [e-mail] (Juergen "Rally" Fischer)   =:)